1. Field of the Invention
The present invention relates to a semiconductor device provided with an ESD circuit, and more particularly to a semiconductor device provided with an ESD circuit which is structured to achieve a high integration of the semiconductor device.
2. Description of the Prior Art
Semiconductor devices may be exposed to high voltage for various reasons. Where a semiconductor device, in particular, a MOS device, is exposed to high voltage, a gate break phenomenon or a junction spiking phenomenon may occur, thereby resulting in a complete break of the device. Although the device itself may only be slightly damaged due to the exposure to high voltage, its reliability is greatly reduced.
In order to avoid such a problem, a high voltage electrostatic discharge (ESD) circuit has recently been proposed.
The ESD circuit should have a space of 5 .mu.m or more between the gate of its data input/output pull-up/down transistor and its contact arranged adjacent to the gate.
Such an ESD circuit will now be described in conjunction with FIG. 1.
FIG. 1 illustrates the layout of a conventional ESD circuit fabricated on a semiconductor substrate.
As shown in FIG. 1, the ESD circuit includes an active region 1 defined on a semiconductor substrate (not shown). Although not shown, data input/output pull-up/down transistors are formed on a portion of the semiconductor substrate corresponding to the active region 1. A plurality of uniformly spaced contact regions 2 are also defined on the semiconductor substrate within the active region 1. The contact regions 2 are arranged in spaced lines.
Gates 3 of the transistors are also formed on portions of the semiconductor substrate between adjacent lines of the contact regions 2 within the active region 1. That is, the gates 3 are arranged in an alternating manner with respect to the contact regions 2.
As mentioned above, the space between adjacent gate 3 and contact region 2 should be 5 .parallel.m or more. Due to such a space, the elements 2 and 3 occupy a large portion of the semiconductor substrate. In other words, the conventional ESD circuit has a large area where its layout is designed in such a manner that the space of the gate and contact overlapping the active region is 5 .mu.m or more. As a result, problem arises because the chip size increases.